1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the provision and use of wrapper serial scan chains for testing circuitry.
2. Description of the Prior Art
There is a need to provide thorough and efficient testing mechanisms for testing integrated circuits. One known technique for testing integrated circuits uses wrapper serial scan chains to apply input signals to and capture output signals from the inputs and outputs associated with a circuit. In a simple system in which only a single functional block is provided on an integrated circuit, the wrapper serial scan chain may serve to apply input signals to and capture output signals from all of the pins associated with the integrated circuit. With more complicated and modern designs it is becoming increasingly common for several functional blocks of circuitry to be combined together on a single integrated circuit to provide a so called system-on-chip design. Such a design is schematically illustrated in FIG. 1 of the accompanying drawings.
FIG. 1 illustrates an integrated circuit 2 which includes a microprocessor core 4, a vector floating point unit 6, an embedded trace module 8 and a block of user defined logic 10. The modular nature of such designs has the result that different functional blocks of circuitry tend to have their own wrapper serial scan chains associated with them for testing their behaviour. In the example shown in FIG. 1, the microprocessor core 4, the vector floating point unit 6 and the embedded trace module 8 all have associated wrapper serial scan chains 5 for use in the testing of those functional blocks of circuitry. The user defined logic 10 does not have its own wrapper serial scan chain. As illustrated in FIG. 1, the microprocessor core 4 is coupled to each of the other functional blocks 6, 8, 10 within the integrated circuit 2. The microprocessor core 4 has a long wrapper serial scan chain, which might typically be several hundreds of serial scan chain cells (flip flops) in length.
A problem that arises during such testing as the integrated circuits under test increase in complexity and size is that the length of the wrapper serial scan chains tends to increase which has a direct result upon the time required to scan in a full set of test vectors and scan out the results. Furthermore, the testing systems required to deal with long wrapper serial scan chains tend to be more complicated and require greater memory resources. In the example illustrated in FIG. 1, it will be seen that if it is desired to simply test the user defined logic 10 which is coupled to the wrapper serial scan chain of the microprocessor core 4, it is necessary to scan in a set of test vectors to the full wrapper serial scan chain of the microprocessor core 4 so that the appropriate pattern of signals can be applied to the user defined logic and captured from the user defined logic. This is inefficient.